Integrated circuits have experienced continuous rapid growth due to constant improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, allowing more components to be integrated into a given chip area.
The volume occupied by the integrated components is near the surface of the semiconductor wafer. Although dramatic improvements in lithography have resulted in considerable improvements in two-dimensional (2D) integrated circuit formation, there are physical limitations to the density that can be achieved in two dimensions. One of these limitations is the minimum size needed to make these components. Further, when more devices are put into one chip, more complex designs are required. An additional limitation comes from the significant gains in the number and length of interconnections between devices as the number of devices increases. When the number and length of interconnections increase, both circuit resistive-capacitive (RC) delay and power consumption increase.
Three-dimensional integrated circuits (3DIC) were thus formed to address issues raised by increase in circuit densities. The dies are stacked, with wire-bonding, flip-chip bonding, and/or through-silicon vias (TSV) being used to stack the dies together and to connect the dies to package substrates. Circuit probe (CP) testing of advanced semiconductor chips and 3DIC with high device density becomes challenging.